Low Frequency CMUT with Thick Oxide

ABSTRACT

A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to CMUTS and, more particularly, to a lowfrequency CMUT with thick oxide.

2. Description of the Related Art

A capacitive micromachined ultrasonic transducer (CMUT) is asemiconductor-based ultrasonic transducer that utilizes a change incapacitance to convert received ultrasonic waves into an electricalsignal, and to convert an alternating electrical signal into transmittedultrasonic waves.

FIGS. 1A-1B show views that illustrate an example of a prior-art CMUT100. FIG. 1A shows a plan view of CMUT 100, while FIG. 1B shows across-sectional view taken along line 1B-1B of FIG. 1A. As shown inFIGS. 1A-1B, CMUT 100 includes a conventionally-formed semiconductorsubstrate 110, and a post oxide structure 112 that touches the topsurface of semiconductor substrate 110. Post oxide structure 112, inturn, has substrate contact openings 114 that extend completely throughpost oxide structure 112 to expose semiconductor substrate 110.

As further shown in FIGS. 1A-1B, CMUT 100 includes a non-conductivestructure 116 that touches the top surface of semiconductor substrate110, and a conductive structure 120 that touches the top surface of postoxide structure 112 and lies over non-conductive structure 116 to form avacuum-sealed cavity 122. In the present example, conductive structure120 includes a semiconductor structure 124 such as, for example, singlecrystal silicon, and an overlying metal structure 126, such as analuminum copper plate.

In addition, CMUT 100 includes substrate bond pads 130 that lie withinthe substrate contact openings 114 to make electrical connections tosemiconductor substrate 110, and a passivation layer 132 that touchesand lies over post oxide structure 112, conductive structure 120, andthe substrate bond pads 130. Passivation layer 132 has substrate bondpad openings 134 that expose the substrate bond pads 130, and aconductor opening 136 that exposes a region of conductive structure 120which functions as a bond pad. Further, CMUT 100 has an acousticdampening structure 140 that touches the bottom surface of semiconductorsubstrate 110.

In operation, a first bias voltage V1 is placed on semiconductorsubstrate 110, which functions as a first capacitor plate, and a secondbias voltage V2 is placed on conductive structure 120, which functionsas second capacitor plate. Thus, the voltage across the capacitor plateslies across vacuum-sealed cavity 122. When used as a receiver, anultrasonic wave causes conductive structure 120 to vibrate. Thevibration varies the capacitance across the first and second capacitorplates, thereby generating an electrical signal that varies as thecapacitance varies.

When used as a transmitter, an alternating electrical signal appliedacross the biased first and second capacitor plates causes conductivestructure 120 to vibrate which, in turn, transmits ultrasonic waves. Therate or frequency at which conductive structure 120 vibrates depends onthe volume of vacuum-sealed cavity 122, and the stiffness of conductivestructure 120.

In addition to transmitting ultrasonic waves outward, ultrasonic wavesare also transmitted backward towards the bottom surface ofsemiconductor substrate 110. These backward ultrasonic waves canresonate within semiconductor substrate 110 depending on the thicknessof semiconductor substrate 110 and the frequency of operation, and caninterfere with the quality of the resultant image. Acoustic dampeningstructure 140 absorbs and dampens the ultrasonic waves in semiconductorsubstrate 110.

FIGS. 2A-2B show views that illustrate an example of a prior-art CMUTarray 200. FIG. 2A shows a plan view of array 200, while FIG. 2B shows across-sectional view taken along line 2B-2B of FIG. 2A. As shown in theFIGS. 2A-2B example, CMUT array 200 includes three CMUTS 100 in a singlerow.

FIGS. 3A-3N show cross-sectional views that illustrate an example of aprior-art method of forming a CMUT. As shown in FIG. 3A, the methodutilizes a conventionally-formed single-crystal silicon wafer 310.Silicon wafer 310 has rows and columns of die-sized regions, and one ormore CMUTS can be simultaneously formed in each die-sized region. Forsimplicity, FIGS. 3A-3N illustrate the formation of a single CMUT.

As further shown in FIG. 3A, the method begins by forming a post oxidestructure 312 on the top surface of silicon wafer 310 using thewell-known local oxidation of silicon (LOCOS) process. The LOCOS processalso forms a backside oxide structure 314 that touches the bottomsurface of silicon wafer 310 at the same time. Following this, as shownin FIG. 3B, a cell oxide layer 316 is grown on the exposed regions ofthe top surface of silicon wafer 310.

After cell oxide layer 316 has been formed, as shown in FIG. 3C, asilicon-on-oxide (SOI) wafer 320 is fusion bonded to the top surface ofpost oxide structure 312 to form a cavity 322. SOI wafer 320 has ahandle wafer 324, an insulation layer 326 that touches handle wafer 324,and a single-crystal silicon substrate structure 328. Substratestructure 328, in turn, has a first surface that touches insulationlayer 326, and a second surface that touches post oxide structure 312.

Cavity 322, in turn, has a depth that is measured vertically from thetop surface of cell oxide layer 316 to the second surface of substratestructure 328. The thickness of cell oxide layer 316 defines theposition of the top surface of cell oxide layer 316. In addition, theheight of post oxide structure 312 over the top surface of silicon wafer310 defines the position of the second surface of substrate structure328.

The thickness of cell oxide layer 316 is relatively small compared tothe height of post oxide structure 312 over the top surface of siliconwafer 310. As a result, the depth of cavity 322 is substantially definedby the height of post oxide structure 312 over the top surface ofsilicon wafer 310. In addition, substrate structure 328 of SOI wafer 320is fusion bonded to the top surface of post oxide structure 312 ofsilicon wafer 310 in a vacuum to vacuum seal cavity 322.

After substrate structure 328 has been fusion bonded to post oxidestructure 312, as shown in FIG. 3D, handle wafer 324 is removed in aconventional manner, followed by the conventional removal of insulationlayer 326. Next, as shown in FIG. 3E, a patterned photoresist layer 330is formed on the first surface of substrate structure 328. Oncepatterned photoresist layer 330 has been formed, as shown in FIG. 3F,the exposed region of substrate structure 328 is etched to form a CMUTmembrane 332. Patterned photoresist layer 330 is then removed in aconventional manner.

As shown in FIG. 3G, after the removal of photoresist layer 330, apatterned photoresist layer 340 is formed on post oxide structure 312and CMUT membrane 332. Once patterned photoresist layer 340 has beenformed, as shown in FIG. 3H, the exposed regions of post oxide structure312 are etched until silicon wafer 310 has been exposed. Patternedphotoresist layer 340 is then removed in a conventional manner.

Following the removal of photoresist layer 340, as shown in FIG. 3I, ametal layer 342, such as a layer of aluminum copper, is deposited totouch silicon wafer 310, post oxide structure 312, and CMUT membrane332. After this, a patterned photoresist layer 350 is formed on metallayer 342.

Next, as shown in FIG. 3J, the exposed region of metal layer 342 isetched to form semiconductor bond pads 352 that extend through postoxide structure 312 to touch silicon wafer 310, and a metal plate 354that touches the top surface of CMUT membrane 332. Patterned photoresistlayer 350 is then removed in a conventional manner.

As shown in FIG. 3K, after patterned photoresist layer 350 has beenremoved, a passivation layer 356 is formed to touch post oxide structure312, CMUT membrane 332, the bond pads 352, and metal plate 354. Oncepassivation layer 356 has been formed, a patterned photoresist layer 360is formed on passivation layer 356.

After this, as shown in FIG. 3L, the exposed regions of passivationlayer 356 are etched to form openings that expose the semiconductor bondpads 352, and an opening, like opening 136 in FIG. 1A, that exposes abond pad region of metal plate 354. As shown in FIG. 3M, patternedphotoresist layer 360 is then removed in a conventional manner.

Next, the resulting structure is flipped over for processing, andbackside oxide structure 314 is removed in a conventional manner. Forexample, backside oxide structure 314 can be removed using chemicalmechanical polishing. Alternately, backside oxide structure 314 can beremoved using a single-sided wet etch, such as a SEZ etch.

Following the removal of backside oxide structure 314, an acousticdamping structure 362, such as a tungsten epoxy mixture, is depositedonto the bottom side of silicon wafer 310 to form, as shown in FIG. 3N,a CMUT 364. Silicon wafer 310 is then diced to form a number ofindividual die that each has one or more CMUTS 364.

In the present example, cavity 322 has a depth of approximately 0.2 μmand a diameter of approximately 36.0 μm. In addition, CMUT membrane 332,metal plate 354, and the overlying region of passivation layer 356vibrate at frequencies of approximately 10-20 MHz. These frequencies aresuitable for contact or near contact body imaging applications, likeecho cardiograms, but are not suitable for airborne ultrasoundapplications where, for example, the object to be detected, such as thehand motions of a person playing a game, is one or more meters away.

Instead, airborne ultrasound applications require much lowerfrequencies, such as 100-200 KHz. If CMUT 364 were scaled up in size tooperate at these lower frequencies, then CMUT 364 would require a largercell diameter (e.g. increasing from about 36 μm to about 1 mm-2 mm), athicker CMUT membrane 332 (e.g. increasing from 2 μm to 5 μm-40 μm), anda deeper cell cavity 322 (e.g. increasing from 0.2 μm to 1 μm-12 μm). Adeeper cell cavity is required to accommodate the atmospheric deflectionof CMUT membrane 332, which can be on the order of several microns. Forproper CMUT operation, CMUT membrane 332 should not touch the bottomsurface of cavity 322, but rather be a fixed distance of one or moremicrons above the bottom surface of cavity 322.

Since the height of post oxide structure 312 substantially determinesthe depth of cavity 322, scaling up CMUT 364 requires that post oxidestructure 312 have a height above the top surface of silicon wafer 310of approximately 1 μm-12 μm, or a total thickness of 2 μm-24 μm.However, forming a post oxide structure with a thickness that exceedsapproximately 5 μm (or heights that exceed 2.5 μm) is difficult toaccomplish because the rate of oxide growth slows dramatically when thethickness of the post oxide structure approaches 5 μm.

As a result, it is difficult to scale up CMUT 364 to accommodate theselower frequencies. Thus, there is a need for an approach to forming lowfrequency CMUTS for airborne ultrasonic applications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B are views illustrating an example of a prior-art CMUT 100.FIG. 1A is a plan view of CMUT 100. FIG. 1B is a cross-sectional viewtaken along line 1B-1B of FIG. 1A.

FIGS. 2A-2B are views illustrating an example of a prior-art CMUT array200. FIG. 2A is a plan view of array 200. FIG. 2B is a cross-sectionalview taken along line 2B-2B of FIG. 2A.

FIGS. 3A-3N are cross-sectional views illustrating an example of aprior-art method of forming a CMUT.

FIGS. 4A-4B are views illustrating an example of a CMUT 400 inaccordance with the present invention. FIG. 4A is a plan view of CMUT400. FIG. 4B is a cross-sectional view taken along line 4B-4B of FIG.4A.

FIGS. 5A-5B are views illustrating an example of a CMUT array 500 inaccordance with the present invention. FIG. 5A is a plan view of array500. FIG. 5B is a cross-sectional view taken along line 5B-5B of FIG.5A.

FIGS. 6A-6R are cross-sectional views illustrating an example of amethod of forming a CMUT in accordance with the present invention.

FIGS. 7A-7B are views illustrating an example of a CMUT 700 inaccordance with an alternate embodiment of the present invention. FIG.7A is a plan view of CMUT 700. FIG. 7B is a cross-sectional view takenalong line 7B-7B of FIG. 7A.

FIGS. 8A-8D are cross-sectional views illustrating an example of amethod of forming a CMUT in accordance with an alternate embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 4A-4B show views that illustrate an example of a CMUT 400 inaccordance with the present invention. FIG. 4A shows a plan view of CMUT400, while FIG. 4B shows a cross-sectional view taken along line 4B-4Bof FIG. 4A. As described in greater detail below, CMUT 400 utilizesthick oxide to increase the size of the cavity which, in turn, allowsthe CMUT to receive and transmit low frequency ultrasonic waves.

As shown in FIGS. 4A-4B, CMUT 400 includes a semiconductor substrate 410that has a bottom surface 412 and a top surface 414, where the topsurface 414 lies in a plane 415. Semiconductor substrate 410, which isconductive, can be implemented with, for example, single-crystalsilicon.

In addition, CMUT 400 also includes a post structure 420 that touchesthe top surface 414 of semiconductor substrate 410 such that no portionof post structure 420 lies below plane 415, and no non-conductive regionlies below plane 415 and touches the bottom surface of post structure420. Further, post structure 420, which is non-conductive, laterallysurrounds a cell region 422 of the top surface 414 of semiconductorsubstrate 410. In addition, no conductive structure extends through poststructure 420.

As further shown in FIGS. 4A-4B, CMUT 400 includes a non-conductivestructure 424 that touches the cell region 422 of the top surface 414 ofsemiconductor substrate 410. In addition, non-conductive structure 424,which can be implemented with a layer of oxide, is laterally surroundedand touched by post structure 420.

CMUT 400 also includes a conductive structure 430 that touches the topsurface of post structure 420, and lies directly vertically overnon-conductive structure 424 to form a cavity 432 that lies verticallybetween non-conductive structure 424 and conductive structure 430. Inthe present example, conductive structure 430 includes a semiconductorstructure 434 such as, for example, single-crystal silicon, and anoverlying metal structure 436, such as an aluminum copper plate.

As further shown in FIGS. 4A-4B, CMUT 400 includes a passivation layer442 that touches and lies over post structure 420 and conductivestructure 430. Passivation layer 442, which is non-conductive, has aconductive opening 446 that exposes a region of metal structure 436 thatfunctions as a bond pad. In addition, CMUT 400 includes a metal bond padstructure 450 that touches the bottom surface 412 of semiconductorsubstrate 410.

In operation, a first bias voltage V1 is placed on semiconductorsubstrate 410, which functions as a first capacitor plate, and a secondbias voltage V2 is placed on conductive structure 430, which functionsas second capacitor plate. Thus, the voltage across the capacitor plateslies vertically across cavity 432.

When used as a receiver, an ultrasonic wave causes conductive structure430 to vibrate. The vibration varies the capacitance across the firstand second capacitor plates, thereby generating an electrical signalthat varies as the capacitance varies. When used as a transmitter, analternating electrical signal applied across the biased first and secondcapacitor plates causes conductive structure 430 to vibrate which, inturn, transmits ultrasonic waves.

One of the advantages of CMUT 400 is that the volume of cavity 432 issubstantially greater than the volume of cavity 122 because poststructure 420 has a height above the top surface of semiconductorsubstrate 410 that is significantly larger that the height of post oxidestructure 112 above the top surface of semiconductor substrate 110. Theincreased volume allows CMUT 400 to accommodate the low frequencysignals required by ultrasonic airborne imaging applications.

FIGS. 5A-5B show views that illustrate an example of a CMUT array 500 inaccordance with the present invention. FIG. 5A shows a plan view ofarray 500, while FIG. 5B shows a cross-sectional view taken along line5B-5B of FIG. 5A. As shown in the FIGS. 5A-5B example, CMUT array 500includes three CMUTS 400 in a single row. In addition, in the presentexample, laterally adjacent CMUT membranes 434 are separated by 50 μm.

FIGS. 6A-6R show cross-sectional views that illustrate an example of amethod of forming a CMUT in accordance with the present invention. Asshown in FIG. 6A, the method utilizes a conventionally-formedsingle-crystal silicon wafer 610 that has a bottom surface 612 and a topsurface 614, where the top surface 614 lies in a plane 615. In thepresent example, silicon wafer 610 has a low resistivity (e.g., 0.1Ω-cm). Silicon wafer 610 has rows and columns of die-sized regions, andone or more CMUTS can be simultaneously formed in each die-sized region.For simplicity, FIGS. 6A-6R illustrate the formation of a single CMUT.

The method begins by forming a patterned photoresist layer on the topsurface 614 of silicon wafer 610 in a conventional manner. After thepatterned photoresist layer has been formed, the top surface 614 ofsilicon wafer 610 is etched for a predefined time to form two or morefront side alignment marks.

If a wet etchant is used, the resulting structure is rinsed followingthe etch. After the rinse, the patterned photoresist layer isconventionally removed, such as with an ash plus a solvent clean.Following the removal of the patterned photoresist layer, the resultingstructure is cleaned to remove organics, such as with a Piranha etch(e.g., using a solution of 50H₂SO₄:1H₂O₂ @ 120° C. removes approximately240 nm/minute).

Next, the method continues by forming a post structure on the topsurface 614 of silicon wafer 610. As illustrated in FIG. 6A, the poststructure, which is non-conductive, is first formed by growing a thickoxide layer 616 on the top surface 614 of silicon wafer 610 usinghigh-pressure oxidization (HIPOX). In addition, a thick oxide layer 617is simultaneously grown on the bottom surface 612 of silicon wafer 610.

For example, thick oxide layers 616 and 617 can be grown at atemperature in the range of 900° C. to 1200° C. with an operatingpressure of 10 to 20 atm. In the present example, thick oxide layers 616and 617 are grown to each have a thickness of approximately 5.15 μm.After this, a patterned photoresist layer 618 is formed on thick oxidelayer 616 in a conventional manner.

Following the formation of patterned photoresist layer 618, as furthershown in FIG. 6B, the exposed region of thick oxide layer 616 is etchedto form an opening 620 approximately 1.12 mm wide that exposes a cellregion 622 of the top surface 614 of silicon wafer 610, and form a poststructure 624.

For example, a non-polymerizing plasma etch can be used to etch anopening through approximately 4.65 μm of the approximately 5.15 μm thickoxide layer 616. In this example, the slope of the side wall at the endof the non-polymerizing etch is approximately 80° (i.e., the opening isslightly larger at the top than at the bottom), and results from thenatural erosion of patterned photoresist layer 618.

Following this, the remaining approximately 0.5 μm of thick oxide layer616 is removed without damaging the cell region 622 of the top surface614 of silicon wafer 610 using, for example, a wet etchant that ishighly or completely selective to silicon. After this, the resultingstructure is rinsed, and patterned photoresist layer 618 isconventionally removed, such as with an ash plus a solvent clean. Theresulting structure is then subjected to a conventional pre-oxidizationclean.

The top surface of thick oxide layer 616, and thereby the top surface ofpost structure 624, are substantially planar. In addition, the surfaceroughness of thick oxide layer 616, and thereby the surface roughness ofpost structure 624, must be controlled to provide a good bondingsurface. In the present example, the surface roughness is less than 3 ÅRMS.

Following this, as shown in FIG. 6C, a cell oxide layer 634 is grown onthe cell region 622 of the top surface 614 of silicon wafer 610 in aconventional manner to have a thickness of, for example, 0.3 μm. Aftercell oxide layer 634 has been formed, as shown in FIG. 6D, asilicon-on-oxide (SOI) wafer 640 is bonded to the top surface of poststructure 624 to form a cavity 642.

In the present example, SOI wafer 640 is vacuum fusion bonded to poststructure 624 of silicon wafer 610 in a conventional manner so thatcavity 624 has a vacuum, followed by an anneal to ensure reliablebonding strength. The anneal can be performed with a temperature in therange of 400° C. to 1050° C. In the present example, the anneal isperformed at 1050° C. immediately after the bonding for approximatelyfour hours. Alternately, other bonding approaches can also be used.

SOI wafer 640 has a handle wafer 644, an insulation layer 646 thattouches handle wafer 644, and a single-crystal silicon substratestructure 648. Substrate structure 648, in turn, has a firstsubstantially-planar surface that touches insulation layer 646, and asecond substantially-planar surface that touches post structure 624. Inthe present example, insulation layer 646 has a thickness of 1.1 μm, andsubstrate structure 648 has a thickness of 14 μm.

As shown in FIG. 6E, after substrate structure 648 has been bonded topost structure 624, handle wafer 644 is removed in a conventionalmanner. For example, handle wafer 644 can be removed by first grindinghandle wafer 644 down to a thickness of approximately 150 μm. In thepresent example, a four hour anneal at 1050° C. is next performed,followed by a wet etch, such as with a solution of KOH or TMAH, toremove the remainder of handle wafer 644.

After handle wafer 644 has been removed, insulation layer 646 is removedin a conventional manner. For example, insulation layer 646 can beremoved using a wet HF etchant that is highly selective to silicon, orchemical mechanical polishing. The wet etch of insulation layer 646could be performed using a single-sided wet etch, such as a SEZ etch bySEZ Austria GmbH, Draubodenweg 29, A-9500 Villach, Austria.

Once insulation layer 646 has been removed, the center region ofsubstrate structure 648 is pulled towards the bottom surface of cavity642 by approximately 4 μm due to the vacuum in cavity 642 and theeffects of atmospheric pressure. To avoid the possibility that substratestructure 648 could be bonded to the top surface of non-conductivestructure 634 during the second four hour anneal, the second four houranneal is performed prior to the wet etch of the final 150 μm Sisubstrate remaining after the initial back grind process step, and thesubsequent wet etch of insulation layer 646.

Following the removal of insulation layer 646, a patterned photoresistlayer is formed on the first surface of substrate structure 648 in aconventional manner. Once the patterned photoresist layer has beenformed, the exposed regions of substrate structure 648 are etched, suchas with a plasma etch, to expose the alignment marks.

Alternately, a conventional Bosch etch can be used to expose thealignment marks. Since post structure 624 (which is approximately 5.15μm thick and lies over the alignment marks) is transparent, onlysubstrate structure 648, which is approximately 14 μm thick, needs to beremoved. After the etch, the patterned photoresist layer isconventionally removed, such as with an ash plus a solvent. Followingthe removal of the patterned photoresist layer, the resulting structureis cleaned to remove organics, such as with a Piranha etch.

As shown in FIG. 6F, after cleaning following the removal of thepatterned photoresist layer used to expose the alignment marks, apatterned photoresist layer 660 is formed on the first surface ofsubstrate structure 648 in a conventional manner. Once patternedphotoresist layer 660 has been formed, as shown in FIG. 6G, the exposedregions of substrate structure 648 are etched to form a CMUT membrane662 that lies directly vertically over the cell region 622 of the topsurface 414 of silicon wafer 610.

For example, a conventional Bosch etch with a short Bosch cycle tominimize side wall scalloping can be used to pattern CMUT membrane 662without damaging CMUT membrane 662. After the etch, patternedphotoresist layer 660 is conventionally removed, such as with an ashplus a solvent clean. Following the removal of patterned photoresistlayer 660, the resulting structure is cleaned to remove organics, suchas with a Piranha etch.

As shown in FIG. 6H, after cleaning following the removal of patternedphotoresist layer 660, a metal layer 674, such as a layer of aluminumcopper, is deposited to touch post structure 624 and CMUT membrane 662.In the present example, metal layer 674 is formed to have a thickness of1 μm. Next, a patterned photoresist layer 680 is formed on metal layer674 in a conventional manner.

As shown in FIG. 6I, after patterned photoresist layer 680 has beenformed, the exposed region of metal layer 674 is wet etched to form ametal plate 684 that touches the top surface of CMUT membrane 662. Inthe present example, metal plate 684 has a minimum width ofapproximately 50 μm. Following the etch, the resulting structure isrinsed. After the rinse, patterned photoresist layer 680 isconventionally removed, such as with an ash plus a solvent clean.

After cleaning following the removal of patterned photoresist layer 680,as shown in FIG. 6J, a passivation layer 686, such as a layer of plasmaoxide approximately 0.6 μm thick and an overlying layer of plasmanitride approximately 0.6 μm thick, is deposited on post structure 624,CMUT membrane 662, and metal plate 684. Next, a patterned photoresistlayer 690 is formed on passivation layer 686 in a conventional manner.

After patterned photoresist layer 690 has been formed, the exposedregion of passivation layer 686 is wet etched to form an opening, likeopening 446 shown in FIG. 4A, that exposes a bond pad region on metalplate 684. Following the etch, the resulting structure is rinsed. Afterthe rinse, patterned photoresist layer 690 is conventionally removed,such as with an ash plus a solvent clean. In the present example, afterthe removal of patterned photoresist layer 690, the resulting structureis alloyed at, for example, 400° C. in an ambient of N₂+H₂.

Next, as shown in FIG. 6K, the resulting structure is flipped over forprocessing, and thick oxide layer 617 is removed in a conventionalmanner. For example, thick oxide layer 617 can be removed using chemicalmechanical polishing. Alternately, thick oxide layer 617 can be removedusing a single-sided wet etch, such as a SEZ etch.

Following the removal of thick oxide layer 617, a metal layer 692, suchas 100 Å of titanium and 1 μm of aluminum copper, is deposited onto thebottom surface 612 of silicon wafer 610 to form a CMUT 694. Metal layer692 can also be implemented with other common back side metallizationstacks, such as TiNiAg, TiNiAu, CRAu, or TiAu. Silicon wafer 610 is thendiced to form a number of individual die that each has one or more CMUTS694.

In an alternate method, as shown in FIG. 6L, after the removal ofinsulation layer 646 and prior to the formation of patterned photoresistlayer 660, a metal layer 695, such as a layer of aluminum copper, isdeposited to touch the top surface of substrate structure 648. In thepresent example, metal layer 695 is formed to have a thickness of 1 μm.Next, a patterned photoresist layer 696 is formed on metal layer 695 ina conventional manner.

As shown in FIG. 6M, after patterned photoresist layer 696 has beenformed, the exposed region of metal layer 695 is wet etched to form ametal plate 697 that touches the top surface of substrate structure 648.In the present example, metal plate 697 has a minimum width ofapproximately 50 μm. Following the etch, the resulting structure isrinsed.

In a first variation, as shown in FIG. 6N, after the rinse, the exposedregions of substrate structure 648 are next etched to form CMUT membrane662. After the etch has been completed, patterned photoresist layer 696is conventionally removed, such as with an ash plus a solvent clean.

As shown in FIG. 6O, following the removal of patterned photoresistlayer 696, the method continues as described above with the formation ofpassivation layer 686, except that passivation layer 686 is formed onmetal plate 697 rather than metal plate 684. One advantage of the firstvariation is that the first variation eliminates one masking step.However, a dedicated silicon etch tool may be required to etch siliconwith the exposed aluminum copper of metal plate 697.

In a second variation, as shown in FIG. 6P, following the formation ofmetal plate 697, the resulting structure is rinsed. After the rinse,patterned photoresist layer 696 is conventionally removed, such as withan ash plus a solvent clean. Following the removal of patternedphotoresist layer 696, a patterned photoresist layer 698 is formed onsubstrate structure 648 and metal plate 697 in a conventional manner.

As shown in FIG. 6Q, after patterned photoresist layer 698 has beenformed, the exposed region of substrate structure 648 is etched to formCMUT membrane 662. Following the etch, the resulting structure isrinsed. After the rinse, patterned photoresist layer 698 isconventionally removed, such as with an ash plus a solvent clean.

As shown in FIG. 6R, following the removal of patterned photoresistlayer 698, the method continues as described above with the formation ofpassivation layer 686, except that passivation layer 686 is formed onmetal plate 697 rather than metal plate 684. One advantage of the secondvariation is that step coverage issues associated with depositingaluminum copper and a patterned photoresist layer over the 14 μm step ofpatterned CMUT membrane 662 are eliminated.

FIGS. 7A-7B show views that illustrate an example of a CMUT 700 inaccordance with an alternate embodiment of the present invention. FIG.7A shows a plan view of CMUT 700. FIG. 7B shows a cross-sectional viewtaken along line 7B-7B of FIG. 7A. CMUT 700 is similar to CMUT 400 and,as a result, utilizes the same reference numerals to designate theelements which are common to both CMUTS.

As shown in FIGS. 7A-7B, CMUT 700 differs from CMUT 400 in that poststructure 420 of CMUT 700 includes substrate contact openings 710 thatextend completely through post structure 420 to expose semiconductorsubstrate 410. In addition, CMUT 700 includes substrate bond pads 712that lie within the substrate contact openings 710 to make electricalconnections to semiconductor substrate 410. Further, passivation layer442 of CMUT 700 has openings 714 that expose the substrate bond pads712.

In addition, CMUT 700 includes a backside structure 714 that touches thebottom side 412 of semiconductor substrate 410. Backside oxide structure710, which is non-conductive and can optionally be removed in the samemanner that thick oxide layer 617 is removed, is formed automatically atthe same time that post structure 420 is formed.

FIGS. 8A-8D are cross-sectional views illustrating an example of amethod of forming a CMUT in accordance with an alternate embodiment ofthe present invention. The present method is the same as the methodillustrated in FIGS. 6A-6G, up through the removal of patternedphotoresist layer 660. As shown in FIG. 8A, after the cleaning followingthe removal of patterned photoresist layer 660, a patterned photoresistlayer 810 is formed on post structure 624 and CMUT membrate 662 in aconventional manner.

Once patterned photoresist layer 810 has been formed, as shown in FIG.8B, the exposed regions of post structure 624 are etched to formsubstrate contact openings 812 that expose silicon wafer 610. In thepresent example, the substrate contact openings 812 each has a diameterof 50 μm. If a wet etchant is used, the resulting structure is rinsedfollowing the etch. After the rinse, patterned photoresist layer 810 isconventionally removed, such as with acetone. Following the removal ofpatterned photoresist layer 810, the resulting structure is cleaned toremove organics, such as with a Piranha etch.

As shown in FIG. 8C, after cleaning following the removal of patternedphotoresist layer 810, metal layer 674 is deposited as before to touchpost structure 624 and CMUT membrane 662, and now also lines theopenings 812 to touch the top surface 614 of silicon wafer 610. Next, apatterned photoresist layer 814 is formed on metal layer 674 in lieu ofpatterned photoresist layer 680.

As shown in FIG. 8D, after patterned photoresist layer 814 has beenformed, the exposed region of metal layer 674 is wet etched to formmetal plate 684 as before, and also form substrate bond pads 816 thatlie within the substrate contact openings 812 to make electricalconnections to silicon substrate 610.

Following the etch, the resulting structure is rinsed. After the rinse,patterned photoresist layer 814 is conventionally removed, such as withacetone. After the removal of patterned photoresist layer 814, themethod continues as before with the formation of passivation layer 686,except that openings are also formed in passivation layer 686 to exposethe substrate bond pads 816 as the same time that the opening, likeopening 446 in FIG. 4A, is formed to expose the bond pad region on metalplate 684. In addition, the formation of bond pad structure 692 isomitted, and the removal of thick oxide layer 617 is optionally omitted.

It should be understood that the above descriptions are examples of thepresent invention, and that various alternatives of the inventiondescribed herein may be employed in practicing the invention. Thus, itis intended that the following claims define the scope of the inventionand that structures and methods within the scope of these claims andtheir equivalents be covered thereby.

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 10. (canceled) 11.A method of forming a semiconductor transducer comprising: providingsemiconductor substrate having top and bottom surfaces wherein the topsurface lies in a plane; growing approximately a 5.15 micrometer thickoxide layer on both the top and bottom surfaces of the semiconductorwafer using a high-pressure oxidation (HIPOX) process; wherein the 5.15micrometer thick oxide layer is grown at a temperature in range of 900°C. to 1200° C. with an operating pressure of 10 to 20 atmospheres;forming a patterned photoresist layer on the thick oxide layer on thetop surface of the semiconductor substrate; etching the thick oxidelayer, exposing the top surface of the semiconductor substrate andforming a post structure on the top surface of the semiconductorsubstrate from the thick oxide layer, wherein the post structure havinga top surface, being non-conductive, and laterally surrounding a cellregion of the top surface of the substrate has no portion of the poststructure lying below the plane of the top surface of the semiconductorsubstrate; wherein etching the thick oxide layer comprises: etchingapproximately 4.65 micrometers of the approximately 5.15 micrometerthick layer utilizing a non-polymerizing plasma etch, wherein the slopeof the side wall at the end of the non-polymerizing etch isapproximately 80°, making the opening slightly larger at the top than atthe bottom of the thick oxide layer; and removing the remainingapproximately 0.5 micrometers of the thick oxide layer with a wetetchant that is highly or completely selective to silicon, thus leavingthe cell region on the top surface of the semiconductor substratewithout damage; forming a non-conductive structure that touches the cellregion of the top surface of the semiconductor substrate; and forming aconductive structure that touches the top surface of the post structureand lies directly vertically over the non-conductive structure to form acavity that lies vertically between the non-conductive structure and theconductive structure.
 12. The method of claim 11 wherein the poststructure laterally surrounds and touches the non-conductive structure.13. The method of claim 12 wherein the cavity is under a vacuum.
 14. Themethod of claim 13 and further comprising forming a metal bond padstructure that touches the bottom surface of the substrate.
 15. Themethod of claim 14 wherein no conductive structure extends through thepost structure.
 16. The method of claim 15 wherein the conductivestructure includes: a single-crystal silicon structure; and a metalplate that touches the single-crystal silicon structure.
 17. The methodof claim 13 and further comprising forming a bond pad opening thatextends completely through the post structure to expose the substrate.18. The method of claim 17 and further comprising forming a conductivebond pad structure that lies in the bond pad opening to touch thesubstrate.
 19. The method of claim 18 wherein the conductive structureincludes: a single-crystal silicon structure; and a metal plate thattouches the single-crystal silicon structure.
 20. The method of claim 12wherein no non-conductive structure lies directly vertically between thecell region of the top surface of the substrate and the bottom surfaceof the substrate.